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19-0297; Rev 1; 9/95
NUAL KIT MA ATION HEET EVALU DATA S WS FOLLO
300Msps, 12-Bit DAC with Complementary Voltage Outputs
____________________________Features
o 12-Bit Resolution o 1/2LSB Integral and Differential Nonlinearity o Capable of 300Msps Min Update Rate o Complementary 50 Outputs o Multiplying Reference Input o Low Glitch Energy (5.6pVs) o Single -5.2V Power Supply o On-Chip Data Registers o ECL-Compatible Inputs with Differential Clock
_______________General Description
The MAX555 is an advanced, monolithic, 12-bit digitalto-analog converter (DAC) with complementary 50 outputs. Fabricated using an oxide-isolated bipolar process, the MAX555 is designed for signal-reconstruction applications at an output update rate of 300Msps. It incorporates an analog multiplying function with 10MHz useable input bandwidth. The voltage-output DAC uses precision laser trimming to achieve 12-bit accuracy with 1/2LSB integral and differential linearity (0.012% FS). Absolute gain error is a low 1% of full scale. Full-scale transitions occur in less than 0.5ns. Internal registers and a unique decoder reduce glitching and allow the MAX555 to achieve precise RF performance with over 73dBc of spurious-free dynamic range at 50Msps with fOUT = 3.1MHz, or 62dBc at 300Msps with fOUT = 18.6MHz. The MAX555 operates from a single -5.2V supply and dissipates 980mW (nominal). It comes in a 68-pin thermally enhanced PLCC package capable of accepting a heatsink.
MAX555
______________Ordering Information
PART MAX555CQK TEMP. RANGE 0C to +70C PIN-PACKAGE 68 Thermally Enhanced PLCC
________________________Applications
Direct Digital Synthesis Arbitrary Waveform Generation HDTV/High-Resolution Graphics Instrumentation Communications Local Oscillators Automated Tester Applications
Pin Configuration appears at end of data sheet.
___________________________________________________Simplified Block Diagram
CLK CLK 800
MAX555
LEVEL-SENSITIVE TRANSPARENT LATCH 800
VREF
ROFFSET VOUT DECODED BIT LINES 50 -20mA LGND AVEE 50
12-BIT ECL LINES
VOUT
BYPASS
________________________________________________________________ Maxim Integrated Products
1
Call toll free 1-800-998-8800 for literature.
300Msps, 12-Bit DAC with Complementary Voltage Outputs MAX555
ABSOLUTE MAXIMUM RATINGS
Analog Supply Voltage (AVEE) .................................-7V to +0.3V Digital Supply Voltage (DVEE) ..................................-7V to +0.3V Digital Input Voltage (D0-D11) ...................................-5.5V to 0V Reference Input Voltage (VIN) .................................0V to +1.25V Reference Input Current....................................0mA to +1.56mA Output Compliance Voltage (VOC)......................-1.25V to +1.0V Output Common-Mode Voltage (VCM) ................-0.25V to +1.0V Note 1: Typical thermal resistance, junction-to-case RJC = 28C/W. Continuous Power Dissipation (TA = +70C) (without additional heatsink) ..............................................1.3W Operating Temperature Range...............................0C to +70C Junction Temperature Range (Note 1) .................0C to +150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C See Package Information.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVEE = DVEE = -5.2V, VREF = 1.000V, TMIN to TMAX = 0C to +70C, unless otherwise noted.) (Note 2.) PARAMETER DC ACCURACY Differential Linearity Error Integral Linearity Error Absolute Gain Error 12-Bit Monotonicity Output Offset Current Output Leakage Current IOS ILEAK D0-D11 = logic 1, VREF = 1.000V, measured at VOUT D0-D11 = logic 0, VREF = 0V, measured at VOUT 90% to 10%, TA = +25C 10% to 90%, TA = +25C Major carry, TA = +25C 0.1% FSR 0.024% FSR, 1LSB change fOUT = 5MHz, fCLK = 50MHz fOUT = 10MHz, fCLK = 50MHz fOUT = 20MHz, fCLK = 100MHz fOUT = 30MHz, fCLK = 100MHz fOUT = 30MHz, fCLK = 200MHz fOUT = 40MHz, fCLK = 200MHz fOUT = 40MHz, fCLK = 250MHz fOUT = 50MHz, fCLK = 250MHz fOUT = 40MHz, fCLK = 300MHz fOUT = 50MHz, fCLK = 300MHz Bits 0-11 high, TA = +25C DLE1 DLE2 ILE1 ILE2 EG VREF = 1.000V, current out, into virtual ground, end-point linearity VREF = 1.000V, current out, into virtual ground, end-point linearity VOUT VOUT VOUT VOUT -0.012 -0.05 -0.012 -0.05 -1.0 0.003 0.01 0.006 0.01 0.2 Guaranteed 40 3 100 50 A A 0.012 0.05 0.012 0.05 1.0 % Full Scale % Full Scale % Full Scale SYMBOL CONDITIONS MIN TYP MAX UNITS
VREF = 1.000V, voltage out, VOUT/VIN (Note 3)
TIME-DOMAIN PERFORMANCE (Note 4) Fall Time tFALL Rise Time tRISE Glitch Energy Settling Time DYNAMIC PERFORMANCE (Notes 4, 5)
510 450 5.6 4 15 70 70 65 60 56 53 52 51 52 51 10.6
ps ps pVs ns
Spurious-Free Dynamic Range
dBc
Output Noise
nV Hz
2
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300Msps, 12-Bit DAC with Complementary Voltage Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVEE = DVEE = -5.2V, VREF = 1.000V, TMIN to TMAX = 0C to +70C, unless otherwise noted.) (Note 2.) PARAMETER DIGITAL INPUTS Input Current, Logic High Input Current, Logic Low Logic "1" Voltage Logic "0" Voltage DIGITAL TIMING Data Update Rate Data-to-Clock Setup Time Data-to-Clock Hold Time Clock-to-VOUT Propagation Delay LSBs Data-to-VOUT Propagation Delay MSBs Data-to-VOUT Propagation Delay MSBs Decode Delay CONTROL AMPLIFIER Amplifier Input Resistance Multiplying Input Bandwidth Open-Loop Gain Input Offset Voltage OUTPUT PERFORMANCE Full-Scale Output Current Output Resistance Output Capacitance POWER SUPPLIES Analog Power-Supply Current Digital Power-Supply Current Power Dissipation Package Thermal Resistance, Junction to Ambient fD tSU tHOLD tPD3 tPD2 tPD1 tDD RIN BW AVOL VOS IOUT ROUT COUT AIEE DIEE PD TJA Minimum data rate = DC (Note 6) Bypass = 0, clocked mode (Notes 4, 7) Bypass = 0, clocked mode (Notes 4, 7) Bypass = 0, clocked mode (Notes 4, 7) Bypass = 1, transparent mode (Notes 4, 7) Bypass = 1, transparent mode (Notes 4, 7) Bypass = 1, transparent mode (Notes 4, 7) VREF = 1.000V -3dB TA = +25C TA = +25C VREF = 1.000V, RL = 0 VOUT, VOUT VOUT, VOUT AVEE = DVEE = -5.2V AVEE = DVEE = -5.2V 30 110 775 3 -250 19.0 49.5 300 1 1.8 2.0 1.5 2.1 600 800 10 20 0 20.0 50.0 15 46 150 0.98 28 60 190 1.3 825 MHz ps ns ns ns ns ps MHz kV/V V mA pF mA mA W C/W IIH IIL VIH VIL VIH = -0.75V VIL = -1.95V -1.1 -2.0 10 1 -0.75 -1.95 200 2 0 -1.48 A A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX555
250 21.0 50.5
Note 2: All devices are 100% production tested at +25C and are guaranteed by design for TA = TMIN to TMAX as specified. Note 3: The gain-error method of calculation is shown below: Definition: [VMEASURE(FS) - VIDEAL(FS)] x 100 EG(%) = ---------------------------------- VIDEAL(FS) where FS indicates full-scale measurements. EG Method: EG = [(4096 / 4095) VMEASURE - 16(VREF / RIN) (ROUT)] x 100 -------------------------------------------------- % 16(VREF / RIN) (ROUT) = [(4096 / 4095) VMEASURE - 1] x 100 --------------------------------- % 1 where: VREF = 1.000V, RIN = 800, ROUT = 50, VMEASURE = VOUT (FS).
Note 4: Dynamic and timing specifications are obtained from device characterization and simulation testing and are not production tested. Note 5: Spurious-free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within the bandwidth fCLK/2, unless otherwise specified. Note 6: Guaranteed by design. Note 7: Timing definitions are detailed in Figure 2. _______________________________________________________________________________________ 3
300Msps, 12-Bit DAC with Complementary Voltage Outputs MAX555
__________________________________________Typical Operating Characteristics
(VREF = 0.75V, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 50MHz)
MAX555-01
SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 100MHz)
MAX555-02
SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 150MHz)
66 64
MAX555-03
72 70 68 66 64 62 60 0 2 4 6 8
72 70 68 66 64 62 60
68
SFDR (dBc)
SFDR (dBc)
SFDR (dBc)
62 60 58 56 54 52
10 12 14 16 18 20
0
5
10
15
20
25
0
5
10
15
20
25
30
35
40
fOUT (MHz)
fOUT (MHz)
fOUT (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 200MHz)
MAX555-04
SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 250MHz)
MAX555-05
SPURIOUS-FREE DYNAMIC RANGE vs. fOUT (fCLK = 300MHz)
62 60 SFDR (dBc) 58 56 54 52 50 48 46
MAX555-06
68 66 64 SFDR (dBc)
68 66 64 62 SFDR (dBc) 60 58 56 54 52
64
62 60 58 56 54 52 0 5 10 15 20 25 30 35 40 fOUT (MHz)
50 48 0 5 10 15 20 25 30 35 40 45 50 fOUT (MHz)
0
10
20
30 fOUT (MHz)
40
50
60
SPURIOUS-FREE DYNAMIC RANGE vs. fCLK (fOUT ~ 1/16 fCLK)
MAX555-07
3RD HARMONIC DISTORTION vs. VREF VOLTAGE (fOUT ~ 1/5 fCLK)
MAX555-08
2ND HARMONIC DISTORTION vs. VREF VOLTAGE (fOUT ~ 1/5 fCLK)
fCLK = 300MHz fCLK = 200MHz
MAX555-09
74 72 70 SFDR (dB) 68 66 64 62 60 58 50 100 150 200 250 300
-48 -50 -52 3RD HARMONIC (dBc) -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 0.5 0.6 0.7 0.8 fCLK = 300MHz
-48 -50 3RD HARMONIC (dBc) -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 -72 0.5
fCLK = 200MHz
fCLK = 100MHz
fCLK = 100MHz 0.9 1.0
350
0.6
0.7
0.8
0.9
1.0
CLOCK FREQUENCY (MHz)
VREF VOLTAGE (V)
VREF VOLTAGE (V)
4
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300Msps, 12-Bit DAC with Complementary Voltage Outputs
_____________________Pin Description
PIN NAME BYPASS CLK CLK DGND DVEE FUNCTION Disables latching of data when high (ECL input) Data Clock (ECL input) Data Clock Not (ECL input) Digital Signal Grounds -5.2V Digital Power Supplies
_______________Detailed Description
Figure 1's functional diagram shows the MAX555's three major divisions: a digital section, a control-amplifier section, and a resistor-divider network. The digital section consists of a master/slave register, decoding logic, and current switches. The control-amplifier section includes a control amplifier and an array of 23 current sources divided into three groups. The resistor divider scales the currents from these groups to achieve the correct binary weighting at the output. The output of the resistor-divider network is laser trimmed to 50, a key feature for driving into controlled impedance transmission lines. The first group of current sources comprises the six MSBs, D11-D6 (resulting in 15 identical, plus two binary weighted currents), which are applied directly to the output of the resistor-divider network. The second group, bits D5-D3 (three binary weighted currents), is applied to the middle of the divider network. The middle of the network divides the current seen at the output by 8. The third group, bits D2-D0 (three additional binary weighted current sources), is applied to the input of the resistive network, dividing the current seen at the output by 64. Glitching is reduced by decoding the four MSBs into 15 identical current sources and synchronizing data with a master/slave register at every current switch. Data bits are transferred to the output on the positive-going edge of the clock, with the BYPASS input asserted low. In the asynchronous mode with the BYPASS input asserted high, the latches are transparent and data is transferred to the output regardless of the clock state. All digital inputs are ECL compatible. The clock input is differential. The control amplifier forces a reference current, which is replicated in the current sources. This reference current is nominally 1.25mA. It can be supplied by an external current source, or by an external voltage source of 1.000V applied to the VREF input. A reference input of VREF = 1.000V will produce a fullscale output voltage of VFS = -1.000V, where: VFS = 4096 / 4095 x VOUT (code 0) for the VOUT output. The output coding is summarized in Table 1. The DAC's control amplifier has a typical open-loop voltage gain of 85dB, and its gain-magnitude bandwidth is flat up to 10MHz. When the control amplifier is not being used for high-speed multiplying applications, it is recommended that a 0.4F capacitor be connected from LBIAS to AVEE to increase control-amplifier stability and reduce current-source noise.
MAX555
1
2 3 4, 56, 57, 63, 66 5, 55 10, 11, 12, 21-25, 27, 31, 36, 37, 40, 41, 43, 45, 46, 61 13, 14 15, 16 17, 18 19, 49, 51, 52, 53, 68 20, 29, 30, 48 26, 44
N.C.
No Connection
VOUT LGND VOUT TN AGND HS
DAC Outputs Ladder Grounds DAC Output Complements Test Node--internal test point, do not connect Analog Signal Grounds Heatspreader Connections-- bypass with 0.1F to AVEE PTAT-IB Reference Compensation Output (connect bypass capacitor to AVEE) Test node--must connect to AGND -5.2V Analog Power Supplies Analog Reference Voltage Center-Tap Input Analog Reference Voltage Inputs (Kelvin connection) Offset Compensation Input Control-Amplifier PTAT Reference Compensation Input (connect bypass capacitor to AVEE) Ladder-Bias Alternate Compensation Output (connect bypass capacitor to AVEE) Data Words (ECL inputs)
28
ALTCOMPIB
32 33, 34 35 38, 39 42 47
LOOPCRNT AVEE VREF/2 VREF ROFFSET ALTCOMPC
50 54, 58, 59, 60, 62, 64, 65, 67, 6, 7, 8, 9
LBIAS
D11(MSB)- D0(LSB)
_______________________________________________________________________________________
5
300Msps, 12-Bit DAC with Complementary Voltage Outputs MAX555
DIGITAL SECTION LSB (D0) MASTER REGISTER 8 12 INPUTS SLAVE REGISTER 8 I1 CURRENT I2 SOURCES AND I3 SWITCHING NETWORK I3 I2 MSB (D11) 4 4 TO 15 15 DECODER 15 I1 3 3
RESISTOR-DIVIDER NETWORK /8 /8 IO 50 17 LGND 17 3 3 /8 /8 50 VOUT
IO
VOUT
CLK CLK
2
MAX555
BYPASS
LOOPCRNT
VREF/2 400 VREF 1V FS 800 ROFFSET 400
I = VIN/RIN
ALTCOMPC
ALTCOMPIB
800 CONTROL AMPLIFIER AVEE
LBIAS
DVEE
AVEE
AGND
DGND
Figure 1. Functional Diagram
6
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300Msps, 12-Bit DAC with Complementary Voltage Outputs
Table 1. Output Coding
DIGITAL CODE (D11-D0) 000000000000 000000000001 011111111111 100000000000 111111111111 VOUT (V) -0.999756 -0.999512 -0.500000 -0.499756 0 VOUT (V) 0 -0.000244 -0.499756 -0.500000 -0.999756
Timing Information
The MAX555 features a differential ECL clock input with selective transparent operation (BYPASS = 1). It is possible to drive the MAX555 clock single-ended if desired by tying the CLK input to an external voltage of -1.3V (ECL VBB). However, using a differential clock provides greater noise immunity and improved dynamic performance. In the clocked mode (BYPASS = 0), when the clock line is low, the slave register is locked out and information on the digital inputs is permitted to enter the master register. The clock transition from low to high locks the master register in its present state and ignores further changes on the digital inputs. This transition simultaneously transfers the contents of the master register to the slave register, causing the DAC output to change. Figure 2's timing diagram illustrates the importance of operating the MAX555 in the clocked mode. In the transparent mode (BYPASS = 1), both the master and slave registers are transparent, and changes in input data rip-
ple directly to the output. Because the four MSBs are decoded into 15 identical currents, there is a decode delay for these bits that is longer than for the eight LSBs. For the full-scale transition case shown, an intermediate output of 1/16 full-scale occurs until the four MSBs are properly decoded. This decode delay seriously degrades the device's spurious performance. In addition, skew in the timing of the input data also directly appears at the DAC output, further degrading high-speed performance. MAX555 operation in the clocked mode (BYPASS = 0) with a differential clock precludes both of these potential problems and is required for high-speed operation. Since input data can only enter the master register when the clock is low (while the slave register is locked out), data-bus timing skew and the internal MSB decode delay will not appear at the DAC output. The DAC currents are switched only when the clock transitions from low to high, after the internal data stabilizes.
MAX555
Layout and Power Supplies
The MAX555 has separate pins for analog and digital supplies. AVEE and DVEE are connected to each other through the substrate of the IC. These potentials should be derived from the same supply to minimize voltage mismatch, which would cause substrate current flow and possible latchup. Appropriate decoupling is needed to prevent digital-section current spikes from affecting the analog section (Figure 4). It is recommended that a multilayer PC board be used, containing a solid ground and power planes. All analog
CLOCKED MODE BYPASS = 0
TRANSPARENT MODE BYPASS = 1
D0
D11 D0 D11
tSU VOUT tPD2 tPD1 15 16 F.S. CLK
tHOLD
tPD3 1 16 F.S. VOUT tDD VOUT VOUT
Figure 2. Timing Diagram
_______________________________________________________________________________________ 7
300Msps, 12-Bit DAC with Complementary Voltage Outputs
and digital ground pins must be connected directly to the analog ground plane at the MAX555, preferably with a "star connection" at the LGND pins (15 and 16). High-speed ECL inputs, as well as the output from the MAX555, should employ good transmission-line techniques, with terminations close to the device pins. Separate power-supply buses for analog and digital power supplies are recommended as good general practice. Best results will be achieved by bypassing the device pins with high-quality ceramic chip capacitors connected physically close to the pins. reducing the reference voltage from its 1.000V nominal value. At clock frequencies above about 200MHz, the output's third harmonic content is dominated by coupling from the high-speed digital inputs to the output. Reducing the reference voltage at these high clock rates actually increases the third harmonic distortion in the output, since the carrier amplitude drops but the third harmonic level remains relatively constant. The second harmonic distortion of the outputs is shown as a function of clock frequency and reference voltage. It is relatively constant for clock frequencies below about 200MHz at different VREF values. As with the third harmonic distortion, however, the second harmonic distortion also increases at clock frequencies over 200MHz for lower VREF values. Minimize these effects by bypassing the MAX555 heatspreader (pins 26 and 44) to V EE with a good-quality RF chip capacitor. Reducing the swing of the input logic levels and/or decreasing the rise time of the digital signals can also improve the output's harmonic content. Combining these techniques achieves the best results. Some experimentation may be required to optimize the MAX555's performance for a particular application. Figure 3 shows the spectrum analyzer plots of the MAX555 when used in DDS applications. These plots show the MAX555's output spectrum at clock frequencies from 50MHz to 300MHz while producing various output frequencies. Observing the output spectrum while adjusting the reference voltage or varying the logic levels is a sensitive method of optimizing MAX555 performance. The plots shown were obtained with a +0.75V reference voltage with 500mV ECL logic swings.
MAX555
__________Applications Information
Reference Input
The MAX555 uses an internal op-amp circuit to buffer the reference current. The input to the op amp may be driven with a 1.25mA external current source or a 1V external voltage reference. The reference input is the VREF pin. The input impedance to the op amp is 800. As shown in Figure 1, VREF/2 is brought out externally with 400 of impedance to the op amp. These reference inputs can be used to vary the full-scale output for high-speed multiplying applications. ROFFSET must be connected to analog ground. In addition, a 0.1F capacitor should be connected from VREF/2 to analog ground to reduce reference current noise.
Outputs
The analog outputs are laser trimmed to 50. They can be used either as a voltage drive with 50 impedance, or to drive into a virtual null using a transimpedance amplifier. Greater speed is achieved driving into 50 loads. The differential outputs of the MAX555 may be used to drive a balun for conversion to a single-ended output, while at the same time greatly reducing the second-harmonic content of the output.
Typical Application
Figure 4 shows a typical connection. With VOUT used to drive a 50 line, the unused complementary output, VOUT, should also be terminated to 50. A 1V reference voltage at VREF gives a -0.5V full-scale voltage at VOUT (when doubly terminated with 50 on the output). Because some loads may represent a complex impedance, be sure to match the output impedance with the load. Mismatching the impedances can cause reflections that will affect AC-performance parameters. In all applications, the LOOPCRNT pin is always connected to AGND, and compensation capacitors are connected to pins ALTCOMPC, ALTCOMPIB, and LBIAS. The LBIAS compensation is recommended for non-multiplying applications. AC grounding the heat spreader on the package (with pins 26 and 44) reduces digital noise feedthrough and improves the MAX555's spurious performance at high data rates.
Dynamic Performance
The Typical Operating Characteristics graphs show the MAX555's performance when used in direct digital synthesis (DDS) applications for generating RF sine waves. The first six graphs show the MAX555's spurious-free dynamic range (SFDR) for clock frequencies of 50MHz to 300MHz at various output frequencies. The seventh graph shows the SFDR for clock frequencies from 50MHz to 350MHz while producing an output frequency of about 1/16 the clock frequency. The last two graphs show the MAX555's third and second harmonic distortion while producing an output frequency of about 1/5 fCLK for clock frequencies from 100MHz to 300MHz as a function of the reference voltage. The third harmonic content of the output can be reduced at clock frequencies below about 200MHz by
8
_______________________________________________________________________________________
300Msps, 12-Bit DAC with Complementary Voltage Outputs MAX555
OUTPUT SPECTRUM (fOUT = 5MHz, fCLK = 50MHz)
-1 -11 -21 -31 dBM -41 -51 -61 -71 -81 2.3MHz/div dBM -1 -11 -21 -31 -41 -51 -61 -71 -81 4.5MHz/div
OUTPUT SPECTRUM (fOUT = 24MHz, fCLK = 100MHz)
OUTPUT SPECTRUM (fOUT = 9.3MHz, fCLK = 150MHz)
-1 -11 -21 -31 dBM dBM -41 -51 -61 -71 -81 7MHz/div -1 -11 -21 -31 -41 -51 -61 -71 -81
OUTPUT SPECTRUM (fOUT = 30MHz, fCLK = 200MHz)
9.5MHz/div
OUTPUT SPECTRUM (fOUT = 20MHz, fCLK = 250MHz)
-1 -11 -21 -31 dBM -41 -51 -61 -71 -81 12MHz/div dBM -1 -11 -21 -31 -41 -51 -61 -71 -81
OUTPUT SPECTRUM (fOUT = 55MHz, fCLK = 300MHz)
15MHz/div
Measurement Conditions: 10dB/div vertical display, 300Hz video filter, TEK2755AP spectrum analyzer VREF = 0.75V, TA = +25C, unless otherwise noted.
Figure 3. Spectrum Analyzer Plots
_______________________________________________________________________________________ 9
300Msps, 12-Bit DAC with Complementary Voltage Outputs MAX555
VREF 1.000V 0.1F POWER SUPPLY -5.2V
IREF 1.25mA 0.1F 0.1F 0.1F 0.1F
50 LINES
38, 39 VREF 54
35 VREF/2
42 ROFFSET
32 LOOPCRNT
33, 34 AVEE
5 DVEE
55 DVEE
D11 (MSB) D10
-2V -2V -2V -2V 12-BIT ECL DATA WORD -2V -2V -2V -2V -2V -2V -2V -2V DIFFERENTIAL ECL CLOCK
58 59 D9 60 D8 62 D7 64 D6 65 D5 67 D4 6 D3 7 D2 8 D1 9 D0 (LSB) VOUT 2 CLK 13, 14 TERMINATE UNUSED OUTPUT 50 50 VOUT 17, 18 50 LINES
MAX555
LGND
15, 16
-2V -2V -2V
3 CLK 1 BYPASS HS ALTCOMPC 47 ALTCOMPIB 28 LBIAS 50 AGND 20, 29, 30, 48 DGND 4, 56, 57, 63, 66 = ANALOG GROUND
50 PULL-DOWNS
26, 44
0.1F
0.1F
0.1F
0.4F = DIGITAL GROUND
AVEE (-5.2V ANALOG)
Figure 4. Typical Application
10 ______________________________________________________________________________________
300Msps, 12-Bit DAC with Complementary Voltage Outputs
____________________________________________________________Pin Configuration
TOP VIEW
D0 (LSB) CLK BYPASS
MAX555
DGND
DGND
DGND
DVEE
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
N.C. N.C. N.C. VOUT VOUT LGND LGND VOUT VOUT (TN) AGND N.C. N.C. N.C. N.C. N.C. HS
D5
N.C.
CLK
D1
D2
D3
TN
D4
D6
D7
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60 59 58 57 56 55 54 53
D8 D9 D10 DGND DGND DVEE D11 (MSB) TN TN TN LBIAS TN AGND ALTCOMPC N.C. N.C. HS
MAX555
52 51 50 49 48 47 46 45 44
N.C.
LOOPCRNT
ALTCOMPIB
ROFFSET
AGND
VREF/2
N.C.
AGND
N.C.
VREF
VREF
N.C.
N.C.
AVEE
______________________________________________________________________________________
AVEE
PLCC
N.C.
N.C.
11
300Msps, 12-Bit DAC with Complementary Voltage Outputs MAX555
________________________________________________________Package Information
A2 e C
DIM A A1 A2 A3 B B1 C e INCHES MAX MIN 0.180 0.165 0.120 0.090 0.156 0.145 - 0.020 0.021 0.013 0.032 0.026 0.011 0.009 0.050 INCHES MIN MAX 0.385 0.395 0.350 0.356 0.290 0.330 0.200 REF 0.485 0.495 0.450 0.456 0.390 0.430 0.300 REF 0.300 - 0.685 0.695 0.650 0.656 0.590 0.630 0.500 REF 0.470 - 0.985 0.995 0.950 0.958 0.890 0.930 0.800 REF 0.625 - MILLIMETERS MIN MAX 4.19 4.57 2.29 3.05 3.68 3.96 0.51 - 0.33 0.53 0.66 0.81 0.23 0.28 1.27 MILLIMETERS MIN MAX 9.78 10.03 8.89 9.04 7.37 8.38 5.08 REF 12.32 12.57 11.43 11.58 9.91 10.92 7.62 REF 7.62 - 17.40 17.65 16.51 16.66 14.99 16.00 12.70 REF 11.94 - 25.02 25.27 24.13 24.33 22.61 23.62 20.32 REF 15.87 -
B1 D4
B D2
DIM PINS
D3 D1 D A1 A
A3
Q PACKAGE PLASTIC LEADED CHIP CARRIER
NOTES: 1. D1 DOES NOT INCLUDE MOLD FLASH 2. MOLD FLASH OR THE PROTRUSIONS NOT TO EXCEED .20mm (.008") PER SIDE 3. LEADS TO BE COPLANAR WITHIN .102mm (.004") 4. CONTROLLING DIMENSION: MILLIMETER 5. MEETS JEDEC MO047-XX AS SHOWN IN TABLE 6. N = NUMBER OF PINS 7. D4 APPLIES TO THERMALLY ENHANCED PACKAGES ONLY.
D D1 D2 D3 D D1 D2 D3 D4 D D1 D2 D3 D4 D D1 D2 D3 D4
20
28
44
68
12
______________________________________________________________________________________

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